For certain niche applications… this is actually a very good thing.
Case in point. Radiation hardness, the ability of a chip to resist the long term effects of radiation damage is highly related to the cross sectional area of the wires. The shiny efficient circuits we make now with their tiny single digit nanometer surface features… are getting to the point where we’re only working with something a few dozen atoms wide. Which means that when high enough energy radiation slams into that part of a circuit, even if all it does is knock a single atom out place or change its atomic structure by neutron or proton capture or splitting it into two or more new atoms… regardless of the result your damaging an appreciable portion of the circuit and It won’t be able to take much before the cumulative effects of exposure to all the radiation degrades the integrated circuit traces and causes eventual failure. A lot of space grade hardware gets around this with having secondary backup hardware or using FPGAs so damaged silicon can be routed around over time. But this gets expensive to use for everything…
Having a way to build basic components like power management watchdogs and other critical circuitry that doesn’t require a lot of “smarts” but does need to be reliable… definitely could benefit from this sort of technology.
So in effect our complex technology systems will start to exhibit a digital form of "cancer" from excessive radiation exposure? Perhaps not as in something that replicates or spreads but the effects may not be outright failure but very strange errors that are unpredictable and can have huge knock on effects.
You simply can't use digital components in high radiation environments. In borderline cases you can implement fault tolerance. This is a big topic and simple explanations with analogies does nothing besides give an inaccurate picture. The type of radiation (the particle), the speed/energy of each particle, the rate of particles passing through your surface area over time, process node size, process topology, and the details of the circuits themselves all play important roles. In many scenarios where you expect errant bit flips but minimal long term damage. Errant bit flips often put circuits in a state that has no typical entry or exit, so the device latches up and needs a power cycle.
You’ve got a solid point about how I was oversimplifying, but it’s not an “inaccurate picture” it’s just not providing as much detail as is needed to accurately predict real world effects… which unless you’re actually working with radiation environments that where the radiation flux is high enough to have noticeable impact before the hardware becomes obsolete or otherwise gets replaced, it’s not a bad analogy.
I’ve had to talk to plenty of people with various levels of understanding of this, including smart hardware and FPGA types, a few radiation physics people as well, it’s not a well established “discipline” outside of some extremely small teams of engineers responsible for the sort of small batch hardened mil-spec chip fabrication runs that doesn’t really get a lot of public documentation, because while not classified, it’s extremely commercially sensitive since and the things the chips go in are usually classified to some level so there’s not a lot to work with other than some stuff that comes out of detector physics at CERN and a trickle of research papers that have come out over the years from NASA, some old DITC papers, the odd helpfully detailed SBIR grant, and some bits here and there in the occasional physics or semiconductor engineering research papers where someone gets into interesting theoretical modelling or analysis of flown hardware or something like that… it’s a niche within a niche within a niche … and the reason I know anything at all beyond being a space nerd for most of my life that was also a computer geek… is that I decided to create a startup doing space robotics, and it should be no surprise that modern robots worth the cost of putting them in space need a respectable amount of integrated circuits and all sorts of other electronics.
I think your making it seem more complicated than it really is beyond the niche nature of knowledge on the topic. It’s the typical aerospace trade triangle: sophistication vs size and weight vs cost. Except in “miniature” and having implications on software design and development. You can shield the hell out of small sensitive components but that’s going to take up size and add mass, you can get military spec parts that take up barely more room than the normal ones do but that’s going to cost a lot, you can go old school and use simpler circuit designs or larger components but this may save some money on components but increasing the size or weight which will increase the cost to get it into space…
Radiation environments in space ar different than the ones CERN and ITER are dealing with. The constraints and trades are also different (putting stuff in another room is often an option). ITER has a fair number of papers out on the subject with some more on the way.
While it’s similar to the kinds of biological damage that radiation can cause, because the radiation induced damage in DNA does work similarly, the energy from a radiation “hit” breaks bonds in the DNA molecule and causes knock on effects just like in the silicon crystal structures and metalic wires…
The better biological analogy for the slow degradation of the integrated circuits due to radiation exposure would probably be heavy metal poisoning because the damage doesn’t typically spread or multiply like DNA damage and/or cancer does. Heavy metal poisoning “accumulates” it’s a slow buildup of something not meant to be there, which causes increasing problems with biological systems, until something is s disrupted by the heavy metal concentration giving a progression of symptoms until enough has built up and you get fatal symptoms.
Edit: Simple example/comparison
Everyone can (and we sadly have plenty of evidence for this) tolerate a fair bit of lead with an LD50 of 4500 to 5500 mg/kg or and a little bit of mercury with various mercury salts having an LD50 from 6-200 mg/kg, (LD50 is the abbreviation for "lethal dose, 50%", The LD50 for a substance is the dose required to kill half the members of a population.). Two heavy metals, two different levels of "exposure risks".
Similarly the metal & doped semiconductors of an integrated circuit have have different sensitives to different kinds of radiation damage. Metal interconnects will tolerate radiation differently than the silicon which is different again to the insulation substrate...
A Heavy ion, like a stray iron nucleus, (https://en.wikipedia.org/wiki/HZE_ion) is going to just dump a lot of energy and screw up a chunk of the atoms in the area around of whatever and wherever it hits, its like the mercury salts, you cant take a lot of hits like that, and fortunately they are statistically rare.
Higher energy protons, like cosmic ray protons, can cause proton induced transmutation which will slowly turn the atoms you want into the atoms you don't want, and can cause the silicon transistors themselves to change similar to how we can (and sometimes do) use neutrons to dope semiconductors in the first place (https://en.wikipedia.org/wiki/Doping_(semiconductor)#Neutron...)
Lower energy protons, and high energy electrons and positrons, can also lead to a slow buildup of electrical charges which can cause dielectric breakdowns and other unwanted effects, which can depending on what is involved and how it happens the cause of intermittent or permanent effects.
Three different kinds of radiation, three different exposure disks. They are each like different "poisons", and the total exposure, the total absorbed dose of each of them accumulates over time... until one or more of them cause something critical to happen and render the hardware inoperable.
But I checked and got second sources that matched close. So I rounded down from 5670mg/kg to a more easily to do mental math with 5500mg/kg.
It turns out the amount of lead required to kill you directly from lead poisoning is… quite a lot! But that’s kill you… your probably going to have some other lead poisoning related health problems well before that.
Yeah, since lead accumulates in the body, I can imagine that a lifetime of exposure from significant sources like water pipes and all the other ways Roman’s were using lead, will just slowly add up until it reaches these sorts of levels, one microgram at a time until you’ve got like two tenths of a kilo of lead in you and a few organs are starting to struggle.
Am I reading that correctly? For $50 you get ~1,000 transistors worth of die space, and it comes in a package? Are there any other limitations? Full-custom analog design if you wanted?
efabless gives 10 mm^2 of project space and the 130nm process node allows for 170kgates to 210kgates per mm^2. That translates to 1.7M-2.1M gates per chip.
It's also unsuitable if you want to keep your design private. Basically, the way this works is that all the different designs are placed on a single chip, with address pins to connect your design to the io pins. This means that everyone participating will have access to all functionality. You essentially buy a single tile in a shared chip.
This is also why it can be done so cheaply. Making 500 copies of 1 chip is way easier than 1 copy each of 500 different chips.
And even then, 130nm is basically the cutting edge from the early 2000s. Cutting edge fabs now are around 3nm. Now, "this node is X nm" has become a marketing term with little correlation to actual transistor size, but from what I've seen, my understanding is you can expect two order of magnitude of difference in density, clock frequency, etc between a 130nm node and a 3 nm one.
I suspect you'd get better performance from a cutting-edge FPGA than from one of these open processes.
I'm no happy to say that. I want them to win! But it looks like they have a lot of catching up to do.
And with Skywater there have been occasional free shuttles (efabless), where they will take your (very small) opensource design and fab it for you on a shared wafer
The process is somewhat well understood, it's the implementation that has so many levels of perfect process and perfect components that makes tsmc a wonder of the world.
The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)