Am I reading that correctly? For $50 you get ~1,000 transistors worth of die space, and it comes in a package? Are there any other limitations? Full-custom analog design if you wanted?
efabless gives 10 mm^2 of project space and the 130nm process node allows for 170kgates to 210kgates per mm^2. That translates to 1.7M-2.1M gates per chip.
It's also unsuitable if you want to keep your design private. Basically, the way this works is that all the different designs are placed on a single chip, with address pins to connect your design to the io pins. This means that everyone participating will have access to all functionality. You essentially buy a single tile in a shared chip.
This is also why it can be done so cheaply. Making 500 copies of 1 chip is way easier than 1 copy each of 500 different chips.
