"RISC-V" isn't an organization that can "move to multi-chip modules". RISC-V is a foundation which essentially publishes a couple of PDF files (the user spec and priv spec) and organizes a bunch of other stuff around reference hardware designs, simulators and the software toolchain.
All of this is BSD licensed, so anyone can pick it up and manufacture chips based on the specification or by modifying one of the reference designs. Note that the largest part of designing and building a chip is not the choice of ISA (that's probably well under 10% of it).
What you may want to know is whether any manufacturers are going to make modular RISC-V chips. None of them to my knowledge. But most of them are currently focusing on the ARM space (embedded, IoT, AI, etc.) including this particular design.
The nice thing is that software and work on a RISC-V toolchain can now be much more common for vendors that elect to use RISC-V, though it remains to be seen how well the actual manufactured chip variation gets supported like instruction set extensions, peripherals, and configurations for many cores. ARM had some motivation to help ease the customization pain for tooling for their IP licensees, so I'm curious if RISC-V support will be more like ARM or more like early UNIX vendors.
Like a lot of chip desicions, this one is based on the effects of the process node in question. So the answer is probably when a company gets to TSMC 7nm while being capable of the high end bonding on the package substrate between chips, at a per chip gate count probably close to the ryzen cpu chips. Before then, it doesn't really make sense.
MCM is a old trick in the toolkit, eg Intel x86 and POWER chips have used it on and off over the years, as have various game consoles. The downside is the cost and complexity of packaging, and the power required for inter-module communication. Many of the past usages have been to closely couple a die from a DRAM process and another die from a logic process. It's not obvious that MCMs are becoming more popular on average in the future.
It allows for easy scaling of CPU designs as well as increasing yield by making smaller components that have overall lower defect rates.
hat seems like the logical next move for most CPU chip vendors/designers except for maybe ARM.