and yet all 3 versions of the TPU are ASICs, not FPGAs :) | Hacker News

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hollerith on July 27, 2018 | parent | context | favorite | on: Jeff Dean’s ML System Architecture Blueprint

and yet all 3 versions of the TPU are ASICs, not FPGAs :)

zeusk on July 27, 2018 [–]

and? that only supports the argument of FPGAs over ASICs (unless Google is harboring some deep secret on cheap chip tapeout process).

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