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Microsoft Research is pushing along as well, they just don't publicize it as much.

Azure has already deployed FPGAs (they believe, being able to deploy and make changes including changes to workload on the fly is more beneficial than the efficiency compared to using an ASIC) for networking and accelerated ML (Project Catapult and Project Brainwave).

tbh, I do agree with using FPGAs over ASICs given the speed at which the tech is moving. Google has already cycled through 3 versions of the TPU.




The underlying operation of multiplying a shitload of numbers together hasn't changed at all. Google's revisions have essentially been more and way more multipliers, respectively.

The main problem with FPGAs is having to deal with the vendors and their evil tools. Those people have no idea what good software looks like, and no business being in my cloud. I guess if you're Microsoft and you already have demonstrated a 40-year history of having no taste in software then you'd be OK putting FPGA tooling into a datacenter. I personally wouldn't even execute that stuff in a sandbox, much less allow it to reprogram my platform.


Asic tools are very similar to fpga tools. You always simulate on fpga first before sending off the RTL for an asic.


and yet all 3 versions of the TPU are ASICs, not FPGAs :)


and? that only supports the argument of FPGAs over ASICs (unless Google is harboring some deep secret on cheap chip tapeout process).




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