Multiple real implementations of register VMs have three operand instructions. Lua, Luajit and Guile are examples that I'm familiar with. For that matter, many ISAs feature three operand instructions. Even some of the recent extensions to x86-64 are three operand versions of (some of) the vector instructions.
If you think three-operand instructions aren't common in both hardware and interpreter design, you are simply misinformed.
None of this has anything to do with SSA. SSA IR can be reasonably constructed from any of stack, accumulator, two-operand register or three operand register bytecode. All of the usual optimizations follow from that.
> the VM speed is much faster than with two or multi word ops
While variable length encodings are best avoided, that doesn't rule out three operand instructions. For a good example of an extremely fast interpreter that uses such instructions, have a look at luajit.
> Nobody does that, it's not needed.
That's what the OP was suggesting, so that's what I was discussing.
If you think three-operand instructions aren't common in both hardware and interpreter design, you are simply misinformed.
None of this has anything to do with SSA. SSA IR can be reasonably constructed from any of stack, accumulator, two-operand register or three operand register bytecode. All of the usual optimizations follow from that.
> the VM speed is much faster than with two or multi word ops
While variable length encodings are best avoided, that doesn't rule out three operand instructions. For a good example of an extremely fast interpreter that uses such instructions, have a look at luajit.
> Nobody does that, it's not needed.
That's what the OP was suggesting, so that's what I was discussing.