> In summary, even the best tools won't help a sloppy designer.
Sloppy engineering is bad. But excusing shitty EDA tools by suggesting the engineer is sloppy is not much better. Most EDA tools are crap at DRC (static rules that only cover geometry and physical connections) and user experience. (Most engineers wouldn't have access to very expensive tools that might be better than some.) You talk about FPGAs (I'm an FPGA/Verilog expert); have you ever looked at the logs? It's getting progressively better, but wading through hundreds and thousands of warning and info messages is not exactly the most effective way to tell an engineer that something might be wrong. Sure, you can write scripts, but the tools are shit out-of-the-box in finding problems and communicating them to the engineer. This is one example, but they're equally bad at guiding the engineer to good design practices that reduces faults, as I think they should.
Circuit design tools are worse, and engineers must rely on their experience and keen eye for detail. Some engineers don't have one or both of those. Are they sloppy? Can't the tools be more intelligent to help?
I think that there is a lot to improve in this domain, and I'm trying to do that with PCBmodE. Blaming the engineer and falling into the "digital Stockholm syndrome" isn't the way forward here.
I've used EDA tools (both board design and chip design) for over 30 years, and in that time there's been one constant: what the designers want to accomplish is usually at (or beyond) the limit of what the tools and platforms are capable of. So yes the tools are "shitty" for what we want to accomplish tomorrow. They're superb compared to what we had yesteryear.
You might not like my "sloppy" choice of words. But IMO the difference between good engineers and mediocre ones is exactly what you called a "keen eye for detail".
I agree the tools could be, and should be, a lot better. It's a copout by the tool vendors when they produce "thousands of warning and info messages". And yet the good engineer must wade through those messages. That is part of the necessary "get on with it" attitude.
> In summary, even the best tools won't help a sloppy designer.
Sloppy engineering is bad. But excusing shitty EDA tools by suggesting the engineer is sloppy is not much better. Most EDA tools are crap at DRC (static rules that only cover geometry and physical connections) and user experience. (Most engineers wouldn't have access to very expensive tools that might be better than some.) You talk about FPGAs (I'm an FPGA/Verilog expert); have you ever looked at the logs? It's getting progressively better, but wading through hundreds and thousands of warning and info messages is not exactly the most effective way to tell an engineer that something might be wrong. Sure, you can write scripts, but the tools are shit out-of-the-box in finding problems and communicating them to the engineer. This is one example, but they're equally bad at guiding the engineer to good design practices that reduces faults, as I think they should.
Circuit design tools are worse, and engineers must rely on their experience and keen eye for detail. Some engineers don't have one or both of those. Are they sloppy? Can't the tools be more intelligent to help?
I think that there is a lot to improve in this domain, and I'm trying to do that with PCBmodE. Blaming the engineer and falling into the "digital Stockholm syndrome" isn't the way forward here.