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kingkilr
on Aug 18, 2013
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Update on STM
Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
4buser
on Aug 19, 2013
[–]
Even new Intel Haswell's STM?
sanxiyn
on Aug 19, 2013
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Yes, Intel TSX too has a limited transaction size.
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