Vivado offers some embedded debugging and logic analyzer infrastructure, which allows you to tap into signals within the design and monitor them from the PC. (For instance, the Memory Interface Generator will report its initialisation status to the PC and if something failed it will tell you what). This is done over JTAG, and Vivado will only support that when using a select few JTAG dongles.

If you're happy to create your own debugging infrastructure (which isn't that hard - almost all FPGAs have at least two dedicated IR scancodes specifically for user applications) then you can use any JTAG dongle supported by OpenOCD.