> Additionally, if you want to get super technical (as if there were ever a real delineation between RISC/CISC), both AMD and Intel decode x86 into internal micro-ops which are essentially RISC.
Given that most CISC chips also relied on microcoding and micro-ops, x86 having micro-ops wouldn't have made it anything like RISC as far as the original CISC/RISC debate goes.
The only reason that the "x86 is really RISC because of micro-ops" comes up is because x86 implementations are superscalar, which was supposed to be impossible with RISC chips, so people started coming up with the micro-op fudge to salvage the story that you need RISC to be an advanced modern microprocessor.
The truth is that CISC was never a meaningful category in the first place (it was only ever "not-RISC"), and RISC itself ceased to be a meaningful category around 30 years ago.
> The truth is that CISC was never a meaningful category in the first place (it was only ever "not-RISC"), and RISC itself ceased to be a meaningful category around 30 years ago.
Yeah, I think we're saying the same things. Thus the "(as if there were ever a real delineation between RISC/CISC)". It's an arbitrary delineation that means nothing today.
Given that most CISC chips also relied on microcoding and micro-ops, x86 having micro-ops wouldn't have made it anything like RISC as far as the original CISC/RISC debate goes.
The only reason that the "x86 is really RISC because of micro-ops" comes up is because x86 implementations are superscalar, which was supposed to be impossible with RISC chips, so people started coming up with the micro-op fudge to salvage the story that you need RISC to be an advanced modern microprocessor.
The truth is that CISC was never a meaningful category in the first place (it was only ever "not-RISC"), and RISC itself ceased to be a meaningful category around 30 years ago.