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Totally agree, the complexity of 3D, heterogeneous nodes, and chiplet integration are necessary. Thank you for your efforts, and I wish you great success.

It's just that for over 50 years optimizing transistor pitch in 2D was sufficient to drive demand and investment. The clear winning single path forward provided the exponential growth we've come to expect. I suspect the complexity and uncertainty of this new heterogeneity does not. Underlying system and process simplicity and reliability support overlaying complexity in software and network.

I started in semi with 68020/30 to see the huge jump from 2um to 0.8um and stayed in on the trailing edge of analog down to 28nm. Maybe there is another 40 years of growth, but it feels like even though 3D stacking increases the power law of dimensionality, it may reduce iteration rate more. We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more?




> We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more?

No, probably not, but that's not the point. The point is that now memory and logic (in case of HBM) can be further decoupled, allowing us to use processes optimized for each, instead of having to compromise one for the other. This will allow for cheaper and faster iteration.

You're correct that 3D scaling will likely not go very far, but that's not the key part; the ability to tightly couple heterogeneous dies, allowing for specialization and decoupling of processes, is the key to further scaling.




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