Thanks a lot for the work you do in documenting these chips.
I am a software engineer that mostly sell fullstack skills. After reading your article on the chip that powers Montreal subway, I developed an interest in chip architectures.
I just finished these two books, The Soul of a New Machine by Tracy Kidder and Hackers by Steven Levy, they are historical books on computer design.
If you have other good reads that a web dev can use in testing the waters I would appreciate.
The Mythical Man Month by Fred Brooks is always worth a read. It's now an ancient tome (e.g talk of how much storage space comments take up) but there is a lot of wisdom there and it certainly ticks the historical box. It's one of the only books I re-read regularly.
I'm not sure if it's quite what you're looking for, but Inside the Machine by Jon "Hannibal" Stokes of Ars Technica has a good overview of computer architecture in general, plus detailed looks at some different processors.
From the Introduction:
"Inside the Machine is an introduction to computers that is intended to fill the gap that exists between classic but more challenging introductions to computer architecture, like John L. Hennessy’s and David A. Patterson’s popular textbooks, and the growing mass of works that are simply too basic for motivated non-specialist readers. Readers with some experience using computers and with even the most minimal scripting or programming experience should finish Inside the Machine with a thorough and advanced understanding of the high-level organization of modern computers. Should they so choose, such readers would then be well equipped to tackle more advanced works like the aforementioned classics, either on their own or as part of formal curriculum."
if you want to understand chip architectures, work through the elements of computing systems (aka nand to tetris). it walks you through implementing your own cpu, gate by gate, plus an operating system, compiler, and tetris game, in a way tested to successfully fit inside of a single-semester undergraduate class. their hardware designs are pretty weird (their hdl looks nothing like any hdl you can actually synthesize hardware from, their descriptions of how gates work are oversimplified, and their instruction set architecture is pretty similar to the eclipse that kidder was writing about but completely unlike any current design) but that isn't really important
after completing the work in that book and raising investment capital for your company, you can honestly call yourself a fullstack engineer
— arm —
the best architecture to write assembly for is the arm—the original one, not thumb, which is a bit of a pain—and arm is also only slightly more complex to build than the fake-ass architecture in nand2tetris, and quite a bit faster. if you already know any assembly language, including the nand2tetris one, the best introduction to arm might not actually be any current tutorial but rather the vlsi arm3 datasheet from 01990 https://www.chiark.greenend.org.uk/~theom/riscos/docs/ARM3-d... which has a summary of the instruction set on p.1-7 (9/56) and a fully complete description on pp.3-12 to 3-43 (19/56 to 34/56)
as you probably know, the vast majority of the cpus around you run the arm instruction set or its thumb variant, although amd64 and aarch64 (arm64) are also significant. the current arm architecture reference manual describes all the new instructions that have been added since arm3, as well as thumb, which makes it enormous and intimidating, with a very low signal-to-noise ratio
perhaps the best introduction to writing assembly language in general on current systems is https://www.muppetlabs.com/~breadbox/software/tiny/teensy.ht..., which is not really focused on assembly at all, but on understanding how the interface between the operating system (i386 linux in this case) and user programs work, which just happens to be at the assembly-language level
it's also a lot more fun to read than any of these except maybe kidder and levy
— risc-v —
the risc-v architecture is very similar to arm but simpler; however, it's a little more of a pain to program, and there aren't any high-performance implementations of it out there, something that's likely to change in the next few years. the part of the risc-v manual https://riscv.org/wp-content/uploads/2019/12/riscv-spec-2019... that corresponds to the part of the arm3 manual i recommended above is chapter 2, rv32i base integer instruction set, pp.13–29. this reflects an additional 30 years of computer architecture lessons from arm and its successors, and a lot of those lessons are helpfully explained in the italic notes in the text. geohot livecoded a full implementation of risc-v in verilog on his twitch stream a few years ago, so you can literally implement risc-v in an afternoon: https://github.com/geohot/twitchcore
gcc can compile to risc-v and generates decent code, and linux can run on it, but the risc-v that linux runs on is quite a bit hairier to implement than the rv32i isa; you have to implement the risc-v privileged isa
— if what you're interested in is how varied cpu architectures can be —
weird in a different direction is the tera mta, which has 128 hardware threads and context-switches every clock cycle; the 11¢ padauk pmc251 microcontroller does the same thing (but with only two threads; padauk sells parts with up to four threads)
the tera mta was designed to compete in the vector supercomputer field originally defined by the cray-1, which had a very different architecture; the convex https://news.ycombinator.com/item?id=40979684 was very similar to the cray-1
in a sense, though, the cray wasn't really the first supercomputer; the cdc 6600, also designed by seymour cray, was, and it was arguably the first risc, in 01964
unlike all of these, the burroughs 5500 architecture had no registers, just a stack, and that's what smalltalk, java, and c# are based on
the 12-bit pdp-8 was the first really mass-produced computer, with over 50000 units sold, and its architecture is interestingly different from all of these, too; intersil produced a 4000-gate single-chip version, and the family was popular enough that there are pdp-8 hobbyists even today
most current numerical computation is being done on gpus, and i don't know what to recommend as reading material on gpus, which have bizarrely different instruction set architectures that use a model called 'simt', single instruction, multiple thread. if anyone does, let me know
finally, chuck moore's line of two-stack processors based on forth are a sadly underdeveloped branch of the genealogical tree; koopman's stack computers: the new wavehttps://users.ece.cmu.edu/~koopman/stack_computers/index.htm... goes into their historical development a bit. they had some significant success in the 80s (the novix nc4000 and the harris rtx2000) but the later members of the family (the sh-boom, the mup21, the stillborn f21, the intellasys seaforth 40c18, and the greenarrays ga4 and ga144 chips) have no real users, in part due to malfeasance—after losing a protracted lawsuit with moore, intellasys head dan leckrone now goes by 'mac leckrone', perhaps as a result
there are lots of other interestingly different instruction set architectures out there: s/360, 6502, amd64, pic16, the erim cytocomputer, the thinking machines cm4, the em-4 dataflow machine, the maxim maxq, the as/400, webassembly, vulkan spir-v, the hp 9825 desk calculator, saturn (used in the hp 48gx), etc.
Thanks a lot, I appreciate the effort required to write in detail. I will work through it.
I could not find your email in your HN bio. I wonder if you have any public "queue " people can send interesting things they are working on and perhaps seek for guidance/opinion.
i'll try to help if i notice incoming email from you but i'm pretty terrible at noticing incoming email even when i manage to not accidentally delete it
Thank you for your work, every article brightens my day!
Every time I look at the chips from 70s and 80s, I notice how huge the features are. Was that determined by the current stepper technology at the time, or by the fact that people drew the early designs by hand?
Or am I totally wrong and the chips are always at the limit of the contemporary technology?
The feature size on chips has steadily shrunk from 10 µm for the Intel 8008 to a few nanometers nowadays. The feature size is determined by the limits of contemporary technology, which steadily improves as described by Moore's Law. Many different technological aspects need to improve to shrink the features, from the design techniques to the optics to the chemical processes.
10 is 10,000 nm. "3nm" apparently has a "gate pitch" of 48 nm, that is 0.5% of the size!
I don't know that "gate pitch" is the correct metric, but I do know that modern marketing nodes don't correspond to reality so this is my crude attempt at trying to bring it to physical reality. Not sure if I did it correctly.
> Or am I totally wrong and the chips are always at the limit of the contemporary technology?
I can chime in here. There are many things that determine the feature size.
There is the process limit, yes, and if your needs are simple digital logic, that's often going to be the density limit.
But if you need NOR flash, there's a stability limit around 40nm process node. You can use smaller transistors for everything else, but soon the NOR is most of the chip.
But what if you need a 1 Amp FET in your PMIC? Well, that won't shrink with process node at all, so maybe a cheaper process node is better to use.
Yes, I was referring to 70's and 80's. Even today, I think, there are applications where 150 nm process is perfectly fine - RFID, transportation cards etc.
If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs, so it is expected.
When did transition from hand-drawn to computer-generated designs happen?
You use lots of very small FETs in parallel (and derate the living bejesus out of the SOA curves, because there's no chance that they'll all run at the same temperature.)
Huh? Almost all modern power FETs have positive tempcos. The resulting hotspots (actually hot transistors) are the reason for the SOA curves, and the reason why most modern power FETs don't do well in linear applications.
Really appreciate the work you do on documenting these chips. It's awesome to see how the stuff I only worked with from the programming side works at the hardware level.
Thank you to you and all the others in this thread for your positive comments. I almost didn't write about this chip because it is so obscure, so it is encouraging that people are reading it.
In some ways, the obscurity makes it even more interesting. That's of course not to say that I didn't enjoy your articles about popular chips like the Z80 or any x86 variant as well, I really do. One is interesting because you get fantastic insight into the chips you've been using for so long, the other because it's a glimpse into an unfamiliar world.
I really love these updates. I really appreciate your articles and they've made me go into a deep dive into the history of microchips and IC design in general.
How did you get into this in the first place? From your blog I gather that you used to be in software (or still are).
How did I get into this? It started when I saw the simulation of the 6502 processor from the Visual6502 team [1]. It was very cool, but totally mysterious. I realized that even though I was a programmer and understood the "full stack", I had no idea how a processor chip actually worked. (I'd taken computer architecture courses but there's still a big jump to physical transistors on a chip.)
I started looking at the 6502's circuits and one thing led to another and here I am today, reverse-engineering obscure chips with a microscope :-)
