The full WSI with 10 billion transistors at 180nm has not been taped out yet, I need $100K investment for that. This has 16K processors and a few megabyte SRAM.
I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects.
The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt.
There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.
This sounds exciting but the enormous and confusing breadth of what your bio says you are working on, and the odd unit errors (lowering "a megawatt" to "2 to 3 terawatt), is really harming you credibility here. Do you have a link to a well-explained example of what you've achieved so far?
I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects.
The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt.
There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.