Not my field, but high speed (high frequency) data transmission cables must overcome several factors related to the interferences caused by the current and voltage of surrounding wires through inductance, and also circumvent the signal degradation due capacitance, resistance and others within the wire per se. With nowadays' PCIe gens we would be talking about frequencies around 8Ghz, 16 GHz and the 32 GHz of the next generation.
When motherboards are designed, the interference and signal integrity between traces/lanes needs to be calculated and balanced for to avoid those issues, but I'm not sure could be done effectively with flexible electrical cables at PCIe frequencies.
But lets say the interferences and signal integrity were stable. I suspect that for to reduce the number of wires within the cables needed by the PCIe lanes -for to avoid the width of classical IDE hard drives cables or something rigid?- it would be needed to increase the speed of the data transmission for a serialized cable equivalent to the source PCIe parallelized lanes, with frequencies wildly higher.
So, as alternative we would be talking about an hybrid of optical data cables + clocking electrical wires then? but the latency/synchro introduced by the optical transceivers (that would need to work at higher frequencies than PCIe bus), each manufacturer using more optimal or less optimal optical transceivers from different brands, etc, I suspect that would introduce a new kind of issue invading the users forums (or maybe not, nevertheless I smell it) due such cables.
The matter is, maybe the above could reduce a bit the size of the motherboard, but not the volume occupied by the targeted devices (lets say GPU), it would be just for to repositioning those devices to a new place. so, although I do believe that the technology in general has been stagnant for a few years, in this case, IMHO, the GPUs are the problem, the GPU's manufacturers are not innovating at all, and due that the bricks.
When motherboards are designed, the interference and signal integrity between traces/lanes needs to be calculated and balanced for to avoid those issues, but I'm not sure could be done effectively with flexible electrical cables at PCIe frequencies.
But lets say the interferences and signal integrity were stable. I suspect that for to reduce the number of wires within the cables needed by the PCIe lanes -for to avoid the width of classical IDE hard drives cables or something rigid?- it would be needed to increase the speed of the data transmission for a serialized cable equivalent to the source PCIe parallelized lanes, with frequencies wildly higher.
So, as alternative we would be talking about an hybrid of optical data cables + clocking electrical wires then? but the latency/synchro introduced by the optical transceivers (that would need to work at higher frequencies than PCIe bus), each manufacturer using more optimal or less optimal optical transceivers from different brands, etc, I suspect that would introduce a new kind of issue invading the users forums (or maybe not, nevertheless I smell it) due such cables.
The matter is, maybe the above could reduce a bit the size of the motherboard, but not the volume occupied by the targeted devices (lets say GPU), it would be just for to repositioning those devices to a new place. so, although I do believe that the technology in general has been stagnant for a few years, in this case, IMHO, the GPUs are the problem, the GPU's manufacturers are not innovating at all, and due that the bricks.