I mean, if you have access to the actual Thunderbolt spec saying otherwise then so be it. Personally, I sincerely doubt that the PCIe packets containing USB 2.0 data are specially routed over the USB 2.0 wires like you say since that runs counter to literally everything public about how Thunderbolt 3 works.
Maybe the spec itself doesn't define a maximum bandwidth allocation for DisplayPort packets, but the DisplayPort stream has to come from somewhere and be output somewhere else, and with one single exception, the actual implementations support two HBR2 streams or one HBR3 stream, with each stream obviously being individually capped to 4 lanes at the physical DP interface.
(AFAIK the special mode combines one 4-lane HBR3 stream with a second 2-lane HBR3 stream)
What...? No. There are no PCIe packets, it's completely separate. The USB 2.0 wires are not part of the Thunderbolt specification, it's part of the USB C connector specification. USB C is a physical connector with four high speed lanes, a separate pair of wires for USB 2.0, one for negotiating things and one "extra". Here is a TB3 dock with a USB 2.0 port: https://www.bhphotovideo.com/c/product/1512891-REG/belkin_f4...
This is the same reason you see some adapters using DisplayPort alternate mode have a USB 2.0 port only -- in this case, it's DP packets which occupy the four high speed lanes much like Thunderbolt above.
My understanding is that your average thunderbolt 3 equipment, when running in thunderbolt mode, did not directly pass through any USB traffic. Instead a dock with USB 2 or 3 ports had to contain a USB controller that connects back over PCIe. This was very common, lots of docks have them.
"Titan Ridge, however, would disconnect the USB 2.0 and USB 3.1 hubs immediately upon entry into TBT3 mode."
"USB4 (and Thunderbolt 4) don't do this for the classic USB 1.1/2.0 wires of D+ and D-. When a hub is operating in advanced USB4 mode, classic USB 1.1/2.0 signals still ride through a normal USB 2.0 hub"
"disabling PCIe also means disabling the way that all Thunderbolt 3 docks get to USB 1.1/2.0/3.2 devices at all"
Maybe the spec itself doesn't define a maximum bandwidth allocation for DisplayPort packets, but the DisplayPort stream has to come from somewhere and be output somewhere else, and with one single exception, the actual implementations support two HBR2 streams or one HBR3 stream, with each stream obviously being individually capped to 4 lanes at the physical DP interface.
(AFAIK the special mode combines one 4-lane HBR3 stream with a second 2-lane HBR3 stream)