> Even “OpenPOWER” is an oxymoron; you must pay IBM to use its ISA.
I guess that is also the issue with Power10 here that causes Raptor to go its own way. For SPARC, it mentions the 32-Bit SPARC v8 and says that 64-Bit SPARC v9 is proprietary, which seems weird given that the T1/T2 are based on that SPARC v9, but I guess that just because the CPU Core is licensed under GPL, the ISA itself is still encumbered?
Anyway, that paper is a great read, thanks!
It will have to be seen if this statement will age like milk or like fine wine:
> RISC-V is also 10 to 20 years younger, so we had the chance to learn from and fix the mistakes of previous RISC ISAs
In software, the desire to throw away all the old and start brand new is often a bad idea because a lot of the janky stuff in the old stuff exists for a reason, often not a very obvious one. But no idea how much baggage old ISAs carry that can be truly discarded, achieving high performance is often a messy affair.
> I guess that is also the issue with Power10 here that causes Raptor to go its own way.
I thought avoiding the POWER10 was the result of firmware blobs. [0][1]
"While we applaud the overall extent of source code available for the #POWER10 firmware stack, two key P10-specific firmware components remain closed source at this time. The first is the off-chip OMI DRAM bridge, and the second is the on-chip PPE I/O processor" [2]
For the same reasons RISC-V had to be created. This is documented in the paper Instruction Sets Should Be Free: The Case For RISC-V[0].
0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...