We're targeting hardware compilers. At this point why not just do the Transmeta route again and abstract that last bits of specialty hardware. The Crusoe emulated things like the x86 MMU on it's VLIW hardware.
Example: LDADD is actually 4 operations, the chip emulates an atomic operation for one of the simplest instructions.
Things I'd like to happen that are kind of opposites:
- To be able to run uops programs. Sure Intel says the decoder is great and they gave up on making Itanium performant through compilation. Give us choice. There's no way the hardware decoding of instructions is always the most performant option. GPU manufactures acknowledged their fallibility with lower level frameworks like DX11 and Vulkan, and I hope we'll continue getting lower and lower level access to their hardware as well.
- Maybe the chip manufactures could all support a dual operation mode, their legacy ISAs, and a compatible ISA. Look at all these options we have on the way to a convergent ISA:
The above mentioned Transmeta Crusoe implements an x86 VM. Zilog Z80 is an Intel 8080 with renamed instructions.
The Web Assembly route is too high level, it's still running on top of the OS even. Java is cool as is .Net IR, but they also just use assembly. Give me the flexibility of the Gigatron to target two different ISAs : https://hackaday.com/2019/07/02/emulating-a-6502-in-rom/
We're targeting hardware compilers. At this point why not just do the Transmeta route again and abstract that last bits of specialty hardware. The Crusoe emulated things like the x86 MMU on it's VLIW hardware.
Example: LDADD is actually 4 operations, the chip emulates an atomic operation for one of the simplest instructions.
Things I'd like to happen that are kind of opposites:
- To be able to run uops programs. Sure Intel says the decoder is great and they gave up on making Itanium performant through compilation. Give us choice. There's no way the hardware decoding of instructions is always the most performant option. GPU manufactures acknowledged their fallibility with lower level frameworks like DX11 and Vulkan, and I hope we'll continue getting lower and lower level access to their hardware as well.
- Maybe the chip manufactures could all support a dual operation mode, their legacy ISAs, and a compatible ISA. Look at all these options we have on the way to a convergent ISA:
https://en.wikipedia.org/wiki/Alternate_Instruction_Set
https://hackaday.com/2021/03/26/undocumented-x86-instruction...
The above mentioned Transmeta Crusoe implements an x86 VM. Zilog Z80 is an Intel 8080 with renamed instructions. The Web Assembly route is too high level, it's still running on top of the OS even. Java is cool as is .Net IR, but they also just use assembly. Give me the flexibility of the Gigatron to target two different ISAs : https://hackaday.com/2019/07/02/emulating-a-6502-in-rom/