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Leveraging parallelism on a single multi-core machine has a definite resemblance to leveraging parallelism in a cluster of machines: memory access costs are likely to be non-uniform, for example (the cores on chip X are "closer" to memory region A than the cores on chip Y, etc.)

This paper examines Map/Reduce performance on multi-core/SMP machines:

http://csl.stanford.edu/~christos/publications/2007.cmp_mapr...




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