How do you mean? Measured in cycles embedded devices typically have less latency... | Hacker News

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		tjoff on April 30, 2023 \| parent \| context \| favorite \| on: Fibonacci Hashing: An optimization that the world ... How do you mean? Measured in cycles embedded devices typically have less latency to SRAM.

xxs on April 30, 2023 [–]

You're right, I guess. On devices where the memory (sram) tends not to have its own clock (and there is no OOO), it can effectively be one cpu cycle. PIC and ESP-32 comes to mind. If there is 'extra' not on chip memory, it'd be way worse, of course.

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