Cachelines are 64 bytes on all modern hardware.
They will probably never change this value ever.
Everything fits into 64 bytes if you make the effort.
And if it doesn't you have to use two Arrays of 64 byte Structures and pad the last.
This is non negotiable and I'm completely baffled nobody has mentioned this yet.
I call this law: Ao64bS (did I invent my first law?) :D
But since it’s AMP and not SMP, sharing work across cores doesn’t necessarily work how you expect it to.
128 bytes is perfect 2 x 64! So even if the risk of cache invalidation goes up even if two cores are not writing to the exact same structure the alignment still works!
Good job Apple!
Cachelines are 64 bytes on all modern hardware.
They will probably never change this value ever.
Everything fits into 64 bytes if you make the effort.
And if it doesn't you have to use two Arrays of 64 byte Structures and pad the last.
This is non negotiable and I'm completely baffled nobody has mentioned this yet.
I call this law: Ao64bS (did I invent my first law?) :D