Even with something as clean as RISC-V, you still need a serial computation to determine insn boundaries. Yes it's a whole lot cleaner than x86-64, but in principle very wide insn decode might still be affected.
RISC-V instruction length is in the first two bits of every instruction; 3 of 4 values mean the instruction is 16-bit, the remaining value is for 32-bit.
The complexity this adds to decode is a far cry from the brute-force approach x86 requires.
This negligible impact is weighted against the benefits of higher code density; RISC-V is the most dense ISA, for 32 and 64 bit.
ARM's AARCH64 does in contrast have exceptionally poor code density for a 64bit architecture. This translates in much higher requirements for cache sizes and ROM size, which in turn mean larger area and higher power consumption for a given performance target.
