Three-address designs trade off a larger insn word for fewer MOV insns and a more straightforward use of the register file. ("Compressed" insns are often two-reg special cases of a three-reg insn.) It's true that RISC tends to feature a higher amount of fully-general registers (as opposed to e.g. separate "data" and "address" registers) but that seems to be a separate development, possibly relating to the load-store approach.
They're all related. When you have an accumulator based design with your ALU and registers, that necessitates a two address format. Or else you're not accumulating. If you don't have space next to your ALU except for one register, you're stuck with an accumulator.
