The results are in the freely available PDF, since Sparkfun are nice. I started to wonder where the numbers went, before I came to the very end and the link to the whitepaper. :)
To summarize, here are the findings how to design mouse bites according to their research:
- Hole Diameter: 0.015"
- Hole Center-to-Center Spacing: 0.025"
- Maximum Tab Width: 0.118"
- Holes should extend into the corners of the tab.
This is great! I love when its discovered that such a small yet fundamental part of a process is just done "by feel" and no one has a reasonable answer to the question "but what's the best way". kudos to Nick and Sparkfun for taking that opportunity to explore!
It's a good article. TLDR: you can use even smaller holes than IPC recommendations (large) or internet consensus (somewhat smaller than IPC) for a more consistent break and nicer finished edge. Also keep the tabs small enough for a manual depanelizing tool like Hakko sells.
For production your assembler's opinion should come first though. Differences in panelization can make a big difference in throughput and yield and they are the experts on their machines and processes. Some really good assembly houses will want to control the panelization themselves and will just ask for unpanelized board files.
Sparkfun doesn't sell Chromebooks, and has no special affiliation with Google. They run a store and sell things to customers that want them. They're also really cool folks - I've met a few of them over the years.
No store can be expected to carry everything that anybody might want for anything, and Sparkfun has no obligation to support ChomeOS.
But, why do you phrase this as some sort of negative? They sold a product, and probably retired it because of lack of sales? Is there more to this story?
To be fair, this post seem to be a way to tell a story about how the white paper came about. The white paper itself is actually a separate publication, which should be read with a more rigorous approach.
Unfortunately, imperial measurements are a pretty common thing in the EE field when it comes to boards. A lot of parts are standardized on the 0.1 inch grid that was relatively common for a good 40yrs or so. I think the commonly understood root is the Dual Inline Package (or DIP) that most early ICs used, which was on a 0.1in pitch for a fair time.
Many of the more common packages under JEDEC [0] are all defined on imperial measurements.
Some package footprints can be approximated or closely matched with round metric measurements, but when the part itself is designed to an imperial measurement you "go with the flow".
The "mil" is one one-thousandth of an inch (0.001) and is thought to have originated from it being a "milli"-inch. I think it's an artifact of decimalizing the inch, from what I've read in the past anyways.
I <3 sparkfun and adafruit.