Strictly 4 bits. For the Morello prototype architecture with full CHERI, it’s 1 ... | Hacker News

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		my123 on March 12, 2022 \| parent \| context \| favorite \| on: RISC-V J extension – Instructions for JITs Strictly 4 bits. For the Morello prototype architecture with full CHERI, it’s 1 bit for each 16 bytes region. (capability valid bit)

saagarjha on March 12, 2022 [–]

Of course, CHERI faces very different challenges than MTE does ;)

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