CAS latency is counted in cycles, ram speed has increased, the cycle count has increased, the absolute amount of time passing has not.

It has decreased, but let's say halving a timing within 20-25 years is not exactly the kind of progress people intuitively associate with semiconductors.

What has decreased quite a lot though is the time to transfer, which is of course stacked on top of CL. CPUs always have to fetch a full cache line (usually 64 bytes), and the time to get 64 bytes out of memory has more than halved each generation.

And DDR5 goes even further by moving you to 2 32 byte cache lines per ram stick which should allow that time to reduce even further