> I'm assuming this is for DMA between the two sockets (and potentially) cross-socket PCIe device routing?
It's more than just that. The memory is attached directly to each socket, so for instance you could have 64GB of memory on each socket for a total of 128GB; for a core in one socket to access memory which happens to be attached to the other socket, it has to go through these inter-socket links. More than that, for a core in one socket to access memory in the same socket but which has been cached somewhere in the other socket, the cache coherence traffic has to go through these inter-socket links.
> Turns out one CPU wasn't quite seated correctly and the GPU was in a slot wired to it. I wonder if this architecture avoids that?
No, each PCIe link is wired to only one of the CPU sockets (PCIe is point-to-point, not a bus like classic PCI), or to an auxiliary chip which is wired to only one of the CPU sockets; if that CPU is not seated correctly, what you saw could happen. The architecture which avoids that is the older one in which all CPUs were wired together in a bus, with PCI and memory attached to an auxiliary chip also on that bus.
It's more than just that. The memory is attached directly to each socket, so for instance you could have 64GB of memory on each socket for a total of 128GB; for a core in one socket to access memory which happens to be attached to the other socket, it has to go through these inter-socket links. More than that, for a core in one socket to access memory in the same socket but which has been cached somewhere in the other socket, the cache coherence traffic has to go through these inter-socket links.
> Turns out one CPU wasn't quite seated correctly and the GPU was in a slot wired to it. I wonder if this architecture avoids that?
No, each PCIe link is wired to only one of the CPU sockets (PCIe is point-to-point, not a bus like classic PCI), or to an auxiliary chip which is wired to only one of the CPU sockets; if that CPU is not seated correctly, what you saw could happen. The architecture which avoids that is the older one in which all CPUs were wired together in a bus, with PCI and memory attached to an auxiliary chip also on that bus.