SRAM scaling from 7nm to 5nm is pitiful. While the CPU transistors see 50-70% increases, the SRAM is only shrinking 20-30%.
For chips with massive cache, that isn’t super cost effective (I suspect as a cost saving measure that we’ll see L2/L3 cache moving to a separate chip on a larger process while the rest shrinks down).
For chips with massive cache, that isn’t super cost effective (I suspect as a cost saving measure that we’ll see L2/L3 cache moving to a separate chip on a larger process while the rest shrinks down).