I'm curious if they will keep up the increase in core counts. It might get more difficult to do that unless the new TSMC processes work very well. They probably would have to go to 16 core (2x 8 core CCX) chiplets as I don't think they can easily fit more chiplets into Epyc.
Well you can expect 128 Core from 5nm or 3nm. I would guess 3nm makes more sense from a die size perspective. I imagine Zen 4 on 5nm would be the same as Zen 3 except with 16 Core and the same amount of cache, since the L3 Cache are now shared.
But the problem isn't so much with the Core Count but the TDP per Core. Imagine it is 3W per Core, 128 Core gets to 384W. And that is excluding the IOD.
I imagine they will need to get quite creative with the cooling process to pull that off.... I have heard of in die water cooling, but that sounds like the only option.
