If you have such a costume chip that you optimize on an instruction by instruction level software comparability probably doesn't matter that much.
> So you can either be non compatible and lean or compatible and bloated.
That's a waste overstatement. The profiles are optimized for specific fields already and you have to evaluate if you want to take advantage of all the software and infrastructure around that profile of if you want to redo all the work just so you can cut out a few specific instruction.
You act like as if every company makes its own costume chips with the minimal set of instructions they need, but that is about 0.01% of the market or less. For the waste majority of use case simply not required and standard embedded profile is perfectly reasonable. And the commercial chips and commercial software will also target that profile.
If you really want to redo everything with your costume chips and compilers, software and so on then that's your choice and RISC-V should not prevent that.
> So you can either be non compatible and lean or compatible and bloated.
That's a waste overstatement. The profiles are optimized for specific fields already and you have to evaluate if you want to take advantage of all the software and infrastructure around that profile of if you want to redo all the work just so you can cut out a few specific instruction.
You act like as if every company makes its own costume chips with the minimal set of instructions they need, but that is about 0.01% of the market or less. For the waste majority of use case simply not required and standard embedded profile is perfectly reasonable. And the commercial chips and commercial software will also target that profile.
If you really want to redo everything with your costume chips and compilers, software and so on then that's your choice and RISC-V should not prevent that.