It’s really funny that you asked this because I clicked on the RISC-V “V” extension spec on GitHub, and literally the only thing I read was “you can’t context switch to another CPU with different vector lengths”.

EDIT: Non-layman wording

> Thread contexts with active vector state cannot be migrated during execution between harts that have any difference in VLEN or ELEN parameters.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...