So Intel has lost the price and performance war against the latest Ryzen architecture and has also lost the fab war against TSMC and if the rumors of Apple moving to their own ARM based arch on TSMC node next year come true, then I expect Intel stock to take a serious tank.
That being said, I'm not too worried about Intel, they have such a diverse silicon portfolio(FPGAs, Optane, etc.) that I'm sure they'll be fine in the end.
There are some new dynamics in play for Intel that didn't used to be there. For example, most of the server CPUs used to be bought by conservative data center owners at stodgy companies. Change didn't happen quickly.
Now, you have huge entities like AWS that can, for example, move things like ALB, RDS, SQS, or Aurora off of Intel on little more than a whim.
Basically, the leverage on the customer side is consolidated now, and the barrier to leave you is lower.
Datacenters are the highest-binned parts, and therefore the highest margins.
Whom is Amazon going to sell low-bin Gravitons to? It isn't cost effective to run them, just like it's not cost effective to use low-binned Intel or AMD chips in datacenters. It's intrinsic to the way all chips are manufactured.
Making your own low performance chips makes clear economic sense, as the producer and consumer of all output. But there have been decades of people trying to make their own high-performance chips as both consumer and producer, and they inevitably fail. And it's not super black and white, whose "subsidizing" whom, in the chip business - datacenter purchasers get cheaper chips because Intel can sell lower-binned parts to enthusiasts, while enthusiasts get cheaper parts because datacenters pay more. Same thing is observed for GPUs, product segmentation in chips is a real synergy and not zero sum.
Who knows if that will succeed, for the idiosyncratic reason of the foundry business being separate from the IP business. Did it really just take a corporate reorg? Maybe AMD was right.
I too dismissed the Gravitron cpus for a long time, until today actually when I saw the benchmarks.
Man, I would not know if amazon was bribing anandtech or something, but the gravitron2s are they're wiping the floor here with Intel and Amd when it comes to performance per cost and even holding their own single threaded which I did not expect.
BTW, I generally dislike such discussions of "who is subsidizing whom" because they often miss the obvious point: both "sides" benefit from having a larger market to spread fixed costs over. There is no "subsidy" here. Just regular economies of scale that benefit (at least for first order effects) all the users.
Budget AWS sells you slices of CPU performance rather than leasing you hours of access to a physical chip. They gain/lose on efficiency in that context.
They sell you a second of performance on a system. There's a fair bit of variation in systems even in the same tier, but you're going to pay the same price.
And low bin chips are still going to be more power efficient than the previous generation.
> Datacenters are the highest-binned parts, and therefore the highest margins.
While I recognized that this is indeed the case, I'd not considered some of the recent plays that Apple has been making. Forget those Gravitons. Forget those low volume datacenter ARM chips too. Also forget those high-binned EYPC and Xeon chips.
What happens when those rackmount Mac Pro machines go to Apple silicon? Datacenters are already paying a premium for processors, but these are much better at performance-per-watt, and Apple can afford to cut the prices on the first and second generation ones to make it up in volume and then ratchet up the prices later once they've got the marketshare.
The question about where low-binned Gravitons go to is an interesting one.
But my point on how easy it is now, as compared to the past, for large swaths of customers to move away from Intel, stands. Moving to AMD or some 3rd party ARM provider are options outside of Graviton that can be done quickly.
A lot of datacenter running cost lays in power and cooling (which requires more power). Maybe Gravitons are not that space effective, but they are definitely power effective, so there is a possibility to get a better margin in the long run.
Apple's history is mostly using older designs for the lower end devices. They are completely different chips, not just a lower frequency version of the same part.
> Whom is Amazon going to sell low-bin Gravitons to? It isn't cost effective to run them, just like it's not cost effective to use low-binned Intel or AMD chips in datacenters. It's intrinsic to the way all chips are manufactured.
If they're starting with designs that are very energy/heat efficient then couldn't they fuse off the bad parts of the dies and then glue like 10 of them onto a single interposer and still have a tdp competitive with x86 server parts?
No. First of all, the efficiency is part of the binning process (some chips are just worse than others). But adding the logic to be able to scale to that many die (high speed SERDES, large caches with lots of cache coherency traffic flying around) takes up more power, and doing the engineering for a large interposer where one wasn't needed before, enlarging the package the interposer sits in, etc. is expensive. Gluing together a lot of defective die on an expensive interposer/package is a bad idea from just about every perspective.
TSMC 7nm and Intel 7nm are completely different things. At this point it's unknown how Intel's 7nm process is going to better/worse than TSMC counter-part. For sure 10nm was a disaster, but the next one doesn't have to be.
Recently TSMC uses names like N7 and N5 for their processes, because they're no more related to actual nanometers on chips. Same for Intel, but they stick to their traditional naming.
It's kind of like rating composite armor by how thick a steel plate would have to be to achieve equal protection except in this case every manufacturer decided to use a different type of steel which makes the entire idea pointless.
Some people predict that feature shrinking may end around 2025 with an inability to go below 2nm. If that's the case, Intel (and everyone else) will get time to "catch up" to the latest technology standards around 2030. TSMC may not be able to hold a lead forever, if there is a physics wall that stops additional shrinking.
There will be additional efficiencies to be found, and TSMC may continue to have an edge on a business-process level, but if shrinking stops, I'd expect the market to become as competitive as vehicle manufacturing currently is, by 2040.
TSMC has a current roadmap of Gate All Around 2nm in 2024 ( 3nm GAA in 2022 is increasingly uncertain ), 1.4nm Nanosheet in 2026 and 1nm in 2028. And this isn't just TSMC, Intel CTO just came out yday with similar timeline. Basically the whole industry is moving to GAA and Nanosheet. Anything too far beyond is unknown. But the last conference TSMC has pointed out to having some ideas for 0.7nm in 2030.
The smallest half-adder is just a double fistful of atoms — about a million times smaller than the proposed 2nm GAA logic. The doubling rate is going to slow down, so we’re talking ~20 generations of at least 3+ years, or more. Who the hell knows what things will look like in the year 2100.
Transistors have been manufactured as a 3D structure for more than a decade and they have multiple dimensions. The idea behind process node naming was primarily about how big a planar transistor would have to be to provide the same transistor density. However, since vendors can slap whatever label they want on their process that's what they end up doing.
If you want to compare manufacturing processes then simply compare transistor densities. That way you will avoid the paradox of thinking that the physical limitations of an old transistor design apply to a chip that is using a completely different design. Here is a list of different possible designs [0].
2040 is in 20 years. With mainland China now investing massively in this the competition will be intense no matter what and that's probably the greater long term threat to TSMC.
TSMC did not exist 33 years ago, so 20 years is a very long time especially with the full weight of the Chinese government thrown in.
-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D.
-Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D.
-ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line.
-China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC).
-China’s OSATs are developing more advanced packages.
About 20 years ago China started developing its own 3G flavour as a way to develop its technology and to catch up. People were saying that they were quite far behind and that this might only sell in China (which it mostly did).
But today we see the result of this long term investment with Chinese companies front and centre in cellular an 5G.
I feel that chip manufacturing has shot up to an even higher priority for them now, so I'm thinking that the landscape may look very different from now in 20 years...
I believe N# are names of various process nodes. Shorthand, people refer to something as the "5nm node" but really there may be multiple (processes | nodes | technology nodes | process nodes | process technologies) that are "5nm".
wikichip has five nodes listed under "5 nm lithography process", two of which are TSMC's:
- N5
- N5P
so N1 would be a hypothetical future process that can produce '1nm' "features".
And their previous roadmaps were completely inaccurate in the most recent shrinks which saw shrinks take, what, 5 years rather than 1 year? Have they even gone to 7nm successfully yet?
> feature shrinking may end around 2025 with an inability to go below 2nm
I feel like I've been seeing these "can't shrink further very soon" claims (including the claim of hard, insurmountable physical limits) for about as long as fusion was 20 years away.
around 2025 with an inability to go below 2nm.
Such predictions are "wild guess" but I've not yet seen an expert strongly bet in favor of a complexity/cost wall.
If I remember correctly, a silicon atom and the spacing between them make ~0.2 nm
If you think that starting at 2nm we are getting closer and closer to this physical limit is utterly wrong:
Because what we call 2nm is not a 2nm transistors. Today transistors (7nm) have some parts that are on the hundred of nanometers!
What I would like to know is how much reducing those parts will bring performance? Maybe those parts of a transistor actually matters far less?
Isn’t there still a ton of room for improvement with 3D ICs? And of course power/heat will still be quite important as well although heat in particular gets significantly harder with 3D chips (or at least I think)
Also, being the first doesnt mean you necessarilly win: smaller node size will give poorer wafer yields, giving Intel time to milk older node processes while playing catchup with TSMC.
Intel has been milking those 14nm++++++ processors for so long now that TSMC went screaming past dragging AMD and Apple with them, I'm not seeing an upside for Intel out of any of this and that's before Meltdown.
I'm still smarting about that dropping 3 weeks after we rolled new servers out at work.
I pity Intel a tiny bit because even though they probably got a bit too comfy on price/feature ratio, I think they took the 1st runner blow by being the first to try sub 14nm at a time when no clear path was on sight, and by the time they got knee deep in their failing strategy, other caught up and now everybody is gliding (seemingly) easily toward 7nm.
Times of crisis are also interesting, maybe intel will have to find new ideas to get his status back.
I wouldn't look to FPGAs or Optane to save Intel's bacon. The issue Intel have is that the x86 is their cash cow - since Intel's primary way of selling FPGAs and Optane is bundling it with their CPU. It's all about pricing the full package of products and using their CPU dominance as leverage.
First, Intel and the semiconductor consortium started the garbage definition of a technology node about 10 years ago, when pitch levels stopped following Moore's law.
Now TSMC and all Intel competitors straight up started lying through their teeth. I'm sure what TSMC is calling '5nm' is a complete joke even in face of the horrible redefinition 10 years ago.
Don't believe me? See for yourself:
- nVidia GeForce GTX 1080 Ti was announced in 2016. base clock 1481 MHz, 11.34 TeraFLOPs FP32, on a 471 mm2 die [1].
- Four years later, RTX 3080 Ti, base clock 1905 MHz, 21.1 TeraFLOPs FP32, on a 700 mm2 die [2].
- 21.1 / 11.34 = 1.86x improvement in raw TeraFLOPs.
- 700 / 471 = 1.486x die size increase
- 1905 / 1481 = 1.286x base clock increase
- 1.486 * 1.286 = 1.91x
Conclusion: nVidia could use the bigger die size and the higher base clock to deliver 1.91x the performance using the same 16nm technology node (theoretically). But instead, using the 7nm node, they're delivering even less of a performance bump, 1.86x, when in reality it should've been 7.64x (= 4x * 1.91x, considering two node jumps, and the die-size and base-clock bump).
Keep in mind that with the 2080, they added raytracing acceleration and tensor cores. Both add area and improve performance of specific user cases, but my guess is that they don't show up in that TFlops number.
This is it - you can't just compare FP32 TFLOPS. The newer cards have a ton of extra precisions, custom cores for certain workloads, and on chip memory, all of which use silicon area and transistors, but none of which boost the FP32 TFLOPS metric.
I could design you a chip that is nothing but FP32 multipliers and adders that has, theoretically, a ridiculous TFLOPS per mm^2, but it would be next to useless in any real workload.
The 1080 and the rumored 3080 are not the same architecture: they didn't just get die shrunk.
For the same number of SMs, you're also paying substantial area for the tensor cores, ray tracing acceleration, independent thread scheduling, different I/O to support memory technologies, more NV link, larger caches, etc. That stuff didn't happen for free.
A simply die shrunk 1080 would have had more TFlops than what we have, but it wouldn't be as interesting of a product.
Exactly, the reason for this is that it is an RTX and it has a lot of tensor cores and ray tracing cores which you won't measure by looking at the amount of FLOPS.
Moore's Law really has 2 aspects - scaling and economic. The original quote states: "The complexity for minimum component costs has in-
creased at a rate of roughly a factor of two per year". This basically says things scale at a certain rate (the time frame was changed from a year to 18 months in a later revision), but also that it is cost effective to do so. The scaling is still happening to some extent, but the cost per transistor has flattened out more so. Performance and power efficiency were never part of Moore's law, and are better covered by Dennard scaling
Note that the marketing name is meaningless, has nothing to do with feature sizes. Also note that "Intel 10nm" is denser than "TSMC 7nm" and Intel's planned "7nm" should be denser than "TSMC 5nm".
I've been looking at Huawei gear, Samsung memory as well and its getting a bit scary about how far USA is behind Asian countries in high tech. Meanwhile all undergrads understand FANG companies pay best, it seems crazy.
TSMC and Samsung are based in Taiwan and South Korea, both strong allies of the US. There was a recent FT article on how the real risk is actually their proximity to China and the potential of China taking military action against factories in Taiwan. TSMC is eyeing a factory in Arizona, so there is that, and honestly, Intel isn't that far behind.
Not only military action. China can simply offer the engineers extremely generous offers and invite the talent to them. From what I read in a few places this is what they are doing.
I live in Taiwan and know many engineers who work in Science park (Foxconn, Tsmc, etc.) It is not at all uncommon for Taiwanese engineers looking to work in China because they pay more, but they really don’t want to do that if given a choice. Lots of people work in China for three or four months and return to Taiwan for a two week rest. Taiwan just doesn’t pay very well for engineers and takes advantage of them being citizens of this country.
These same engineers looking to go would rather relocate to Germany or the US than China. Either way there is a serious brain drain going on here where the brightest want to leave. Taiwan is a wonderful place but I question its stability over the next few decades.
It is quite sad how every developed country in the world is practically giving away their advantages to China. All because of short-sighted economics and political incompetence.
Chips are manufactured using equipment that is not made in Taiwan or China. It's primarily made in the USA, Japan and Europe. That same equipment is available to Intel.
In the last 12 months, Intel's net profit was $21,000,000,000.
I don't work for Intel so I don't know, but I'd wager that any chip node that TSMC can produce, Intel can produce as well. Intel has access to the same equipment and plenty of profit to work with. They either choose not to, or, they simply choose not to advertise the capability.
For TSMC, as a foundry, their manufacturing capability is a selling point. For Intel, it is a strategic advantage. It makes sense for TSMC to announce what node they are capable of. It does not make sense for Intel to do so. Intel sells chips based on the chips' capabilities. Not on Intel's manufacturing capabilities.
> Interestingly, however, Intel's CFO has previously admitted that 10nm yields aren't great and will actually be lower in profitability than their older 22nm process
Perhaps, but bringing up a fab production line is (massiveley) expensive. It could just as easily be a business decision to outsource the GPU production to TSMC for the time being, or indefinitely, depending on anticipated volumes.
I'm looking for more than assumptions and inference based on public information. Sure, Intel might not have the capability to build at 5nm even if they wanted to, but a lack of public evidence that they are building at that node does not mean they can't.
> its getting a bit scary about how far USA is behind Asian countries in high tech
Yeah right.
Cambodia, North Korea, Myanmar, Mongolia, Bangladesh, the Philippines, Vietnam, Sri Lanka, India, Laos, Thailand, Nepal, Russia, Afghanistan, Indonesia, Pakistan, Malaysia, Bhutan, Kyrgyzstan, Tajikistan
Which of those are leading the world in "high tech"?
China's only consequential tech company is Huawei. South Korea has Samsung, SK and LG. Taiwan has TSMC, Pegatron, Quanta. Japan has Sony, Nintendo, Canon, Hitachi, Panasonic and one or two others that are relevant.
It's amazing how far ahead the US remains after so many decades.
That's a partial list of large US tech companies. Asia has nothing like it, and that's before getting into the vast number of US software & cloud services companies (Workday, ServiceNow, Splunk, Twilio, Cloudflare, Datadog, Palo Alto Networks, Akamai, etc.), of which Asia has no comparable list.
Besides that, Asia isn't a country, it's silly to pretend they're somehow one unit. They're all competitors. It's equivalent to pretending Europe or Latin America operate as combinations.
Show me the Asia equivalent of AWS (Alibaba's 1/5th size clone?). The world lags embarrassingly, the US has a ten year lead in cloud services.
Tencent is a gaming & entertainment company. Baidu is a languishing search company that never got outside of China. Alibaba is an advertising platform that does nothing special. ByteDance is mostly social media, there's nothing special about that either (see: FB, Twitter, Snap, Pinterest, etc).
China is the only individual country that comes close to competing with the US in tech and they're still well behind in most tech segments and surpass the US in none other than digital payments.
> Japan has Sony, Nintendo, Canon, Hitachi, Panasonic and one or two others that are relevant.
Add Nikon to the list, especially in the context of chip fabbing (They and Canon are one of the few companies that make fab equipment not necessarily of the same caliber as ASML, but similar vein.).
I was told a decade ago by my professor that chip makers were facing an issue with electrons jumping across these tiny circuits, and couldn't go much smaller. I'm continuously surprised.
Excess electrons and holes in silicon spread through spaces on the order of 10nm. Any smaller features will get mixed up.
But that's not really what is happening here. The first thing is that those are feature size, not the size of the dopant region. They are like the size of the pixels on a screen, where the transistors get drawn. The second thing is that this limit is for silicon crystals, and top of line chips are now built in 3D with mixed materials, so you can have an entire crystal that is smaller (at least in one dimension) than that limit.
Gentle reminder that 5nm is a meaningless marketing number that does not represent neither the transistor size no element density, and it does not correlate in any way with all other Xnm production of other companies.
Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond https://semiengineering.com/5-3nm-wars-begin/
Single-thread performance it tied to clock frequency, which cannot go above 5Ghz, so the only thing we'll see is more cores. It is actually blessing in disguise, this is exactly why ancient Core Duos, made in 2007 are still perfectly usable for office applications and even lightweight development.
Where do you get this idea? Single-threaded performance has improved substantially in the past several generations of Intel processors. Single-threaded performance and clock speeds have not been correlated outside of same generation for a while now - like over a decade.
There's are 2.8GHz processors at the top of that benchmark with a 3100 score and one near the bottom with a 539 score, as well as everywhere in between.
Probably he based his opinion on speed of progress. In 2006 you could buy Core 2 Duo at 3.0GHz. Modern processor at 4.5GHz would be maybe just 3 times faster in normal, every day, single thread use which seems like a lot, but isn't too much if you think that CPUs 14 years before Core 2 Duo were clocked at 33MHz and IPC slightly below 1.
My dad uses a computer with C2Q CPU and it's still fast enough for everyday use.
Edit: to be clear, he's still wrong, we had quite untrivial IPC increase during all these years. I just wanted to point out that he's comment probably was based on empirical data.
5% increase per gen for most of the past decade vs. 50% increase per gen when clock speeds were increasing in lock step along with transistor count, but sure.
I've got a 13 year old laptop that runs today's OS's and development software a little slow but ultimately just fine, and if it weren't for a low limit on installed RAM it would be more than "ultimately" just fine.
That would've been absolutely laughable even 10 years ago, much less 20. You'd be lucky to be able to run a then-current OS on 2-3 year old hardware in the 90's through early 2000's.
Of course they are not linearly scalable across generation, but last significant performance improvement was in Sandy Bridge. Let's compare for example i5-2500 and i3-9100, more or less similar chips in terms of the number of cores and cpu freq. Their single thread performance (normalized per GHz) is within 25% from each other. In the last 10 years we've got 25% increase in IPC. If we compare with slightly more modern CPU's such i5-3570 it becomes even more laughable meager 10%. So, yeah we are reaching the limit of IPC, if not reached already.
> Single-thread performance it tied to clock frequency
Within an architecture, yes, but between architectures performance of different usage patterns may vary wildly.
> which cannot go above 5Ghz
this is objectively false. Intel is shipping (limited amounts of) chips that boost over 5GHz, and IBM is shipping its z15 z/architecture CPU which clocks at 5.2 GHz, and shipped its ancestor, the zEC12 CPU clocking in at 5.5Ghz (!), in 2012.
> Single-thread performance it tied to clock frequency
In a very loose sense.
It's clock speed * instructions per clock. But even that is misleading, as the number of instructions per clock is not a fixed quantity and hasn't been for decades now. It's also impacted by the instructions that came before and the ones predicted to come next.
> this is exactly why ancient Core Duos, made in 2007 are still perfectly usable for office applications and even lightweight development
They are suitable because these applications are not very demanding. A Core2Duo at the same clock speed of a modern processor will be much slower.
> cannot go above 5Ghz
Can, and have. But the cost-benefit of increasing clock speeds further is not favorable.
I know how CPU's work. Core 2 might be an extreme example, but IPCs between 10 years old Sandy Bridge and Coffee Lake differs only by 25(!) percent. So yeah, last 10 years, and especially after the Ivy Bridge, Cpu Freq almost linearly tied with the performance.
It is not bizarre at all. I find bizarre, OTOH when people fail to understand the context of the phrase. It is not normal to overspecify a statement, when it is clear what is the obvious meaning: a normal modern consumer-grade CPU in a typical usage environment cannot work at frequencies above 5Ghz. And that is true.
Increasing clock speed will require a different technology than silicon. It's not impossible to think that graphene or carbon nano tubes could allow higher clock speeds.
As you increase clock speed, temperatures approach the surface of the sun.
Besides being hard to cool, it causes chemical, delamination and other changes to the chip, eroding it.
"In 2001, Pat Gelsinger—then Intel‘s CTO—predicted that within a decade the energy density of chips would be equivalent to the surface the sun if nothing was done."
That being said, I'm not too worried about Intel, they have such a diverse silicon portfolio(FPGAs, Optane, etc.) that I'm sure they'll be fine in the end.
My $0.02.