There's an article in Russian about porting V8 and Firefox's SpiderMonkey onto these processors: https://habr.com/ru/company/jugru/blog/419155/

You may gleam some architectural details from the article and the comments.

That was well worth the read. Looks like the pipeline isn't exposed, which is what I'd expect for a VLIW in this role. They've got a some support for speculative loads but it seems pretty small so I'm not surprised they're having trouble adapting to general purpose code.

I'm not sure I understand what you mean by the pipeline being exposed. No processor I'm aware of other than the i860 exposed its pipeline, so I don't know what you mean by that here. Can you elaborate?

Lets say that a load from the L1 data cache takes two cycles. Take the following instruction sequence.

  r1 = 3
  r1 = load(r2) // will return 8
  r3 = r1 + 2

In a typical processor the system will stall or reorder things so that the load completes before the third instruction so the final result in r3 is 10. In an exposed pipeline model the assignment to r3 will happen before the load instruction returns so the final value of r3 will be 5. I don't think this is very common outside VLIW systems but you have some famous ones that have used it there, like the Transmeta Crusoe. And the Mill guys are hoping to use it, basically, though they're calling it phasing and it's not exactly the same thing.