I'm quite confused my Tensil, is the training of the model moved to their chips, or the final model? If the former, then are the chips locked in to whatever model they were built for, e.g. this chip only trains a multi-layer perceptron with n layers? Or are the chips re-programmable or FPGAs? If the latter, don't most models run quite quickly on CPU after training anyways?
It seems like they're selling ASICs. It would be useful in something like an embedded system where you train a model beforehand, deploy it, and then let it go. On top of speed improvements, they're generally more efficient, so something running on battery power could last longer.
Tensil founder here: we take fully trained models, training doesn't happen on our chips. The model architecture is hardened but the parameters can be reprogrammed.
