It’s a hobbyist thing. Useless in corporate setting. I can summon vendor’s field application engineers when I have a problem. Guess what I can do when I have problems with open source toolchain and project’s deadline is coming. Xilinx and Altera will not support 3rd party tools due this liability issue for sure. Time and contributions will not help this venture, the problems are not technical.
Yes, when you are targeting an ASIC and a manufacturing pipeline, you need more support. But not everybody is. In fact, 7+ billion aren't. There is no shame in shipping a low-volume FPGA product, or even in targeting an existing FPGA demo board. Or even a commercial SOC or PC, if it does the job.
Yes. Very talented engineers are paid large sums of money to work on open source compilers when the company's main concern is NOT compilers - Red Hat wants the compilers stable on Linux, and helps out. Same for apple. Etc, etc.
"Open Source" is just somebody else footing the bill because it IS NOT the main business concern - compilers aren't your product differentiator, but you need them to work on your systems, you pay talented engineers to work on them.
This dynamic DOES NOT HOLD for FPGAs. There is no "second source" of Xilinx FPGAs. Nobody will pitch in to help Xilinx because the only people who employ an army of talented people with the direct niche skills needed are their competitors.
F/OSS software is not great once you get past small, single use tools. KiCad became barely useable in Version 5, and it's still a decade behind what we had commercially a decade ago - and there are probably what, 500 PCB designers for every ASIC designer? 50 for every FPGA designer?
Xilinx and Intel fund programs at schools to develop talent they can use to further develop their systems and chips. That's remarkably NARROW.
In short: No, this tool will NEVER achieve critical mass, unless Lattice decides to support it directly - and then it still won't work on Xilinx chips. It is an absolute dead end, because the economics that helped the success story of GCC will not apply.
There is no synthesis engine for VHDL in it that I'm aware of. It will never handle encrypted IP, so you can't just buy a core if you don't have a certain expertise in house.
It's... Useless in most commercial settings. The Symbiyosys tools in a commercial setting are only useful for formal verification. And they have some extreme limitations.
The commercial version of Symbiyosys uses Verific to parse and elaborate designs. The Verific front-end supports Verilog, SystemVerilog and VHDL.
When it comes to formal verification, the Verific front-end and the Yosys Verific backend support a large set of the formal verification primitives of SystemVerilog. (See also the above link.)
