The clock source is typically generated by a phase locked loop from the external crystal oscillator. There's a PLL multiplier and divider value that you can set obtain the desired frequency.
I think the MCU starts running at a low speed from an internal RC oscillator, and then setting up the high speed clock source happens early in the initialization code. This code can be generated by ST's STM32Cube software, which is useful as a reference implementation even if you don't use the generated code in your project.
As mentioned it uses PLL. The chip boots using the internal 8MHz oscillator, and you can then enable the external crystal using code.
The clock configuration is actually a bit complex, you can see an example from the STM32CubeMX configuration code generator tool here: https://imgur.com/S9L6U37
HS means high-speed and is used for the system clock and peripherals, while LS is low-speed and is used for the real-time clock. Peripherals have limits, like the ADC clock is shown to be 36MHz, but the maximum is 14MHz. The tool is not complaining because the ADC was not enabled for that project. Otherwise I would have to change the ADC prescaler, which take values like 2, 4, 6 etc. Thus had I enabled the ADC, I would have been forced to use a prescaler of 6, making the ADC clock 12MHz, below maximum.
To get the maximum ADC frequency of 14Mhz, I would have to lower the system clock to 56Mhz.
Other peripherals, like USB, also has some strict limits.
Pretty much all clocks in modern electronics above a few MHz are generated by PLL synthesis. The synthesizers are referenced to a slower clock crystal or something along those lines. You can go way beyond just multiplication, as well, with fractional synthesis. Check out the Si5351 for a chip that packs a couple of these synthesizers.
Does it use some kind of internal clock multiplier to achieve 72MHz? Would such a magnified 8MHz to 72MHz provide a good stable clock?