Cycle-accurate simulation as a software development vehicle while you wait for the real hardware to become available. Get your software debugged now and you will be good to go when the real chips land.
I think cycle-accurate simulation is critical for developing a RISC-V chip and/or toolchain -- being able to get real feedback from benchmarks, etc.
For functionality testing (to port your software to RISC-V) you probably don't care quite as much about the cycle accurate simulation. An inaccurate simulator would probably just behave the way that a target with a much faster or slower clock speed would behave.
Sure. First step is "make it work". A functional simulator is sufficient for that. If you are working on a compiler back-end, then the ability to see actual pipeline stalls, to run benchmarks, to investigate the impact of various text and data section layouts on cache performance, then a more accurate simulator is useful. Or if you are working on time critical features of the OS, like a context swap, then you definitely benefit from the ability to do a cycle-accurate instruction trace.
What the cycle-accurate simulator buys in end is schedule acceleration for when a mature RISC-V software stack lands. So from an overall RISC-V program-management perspective, this is smart thing. Granted, the audience is small, but the resulting leverage is huge.
Imagine being the PR person having to respond to press that says: "I tried this basic thing on your new chip and it is slow." and having to say: "Just wait until we turn on the optimizer in the C compiler! It will be 35% faster!". Reporter: "Yeah, whatevs." This simulator is all about product launch readiness.
Maybe you aren't the intended audience? Did you even read the article? It's clearly pitched towards researchers and people testing their software on RISC-V
ELI5 what would one accomplish with this.