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I suspect this technique will need a lot of refinement before its actually competitive.

The main trouble with this technique, I suspect, is it doesn't get at the root of where power is really spent. Yes, anything costs power, but is that where all the juice is really going? A famous stat from the P4 days was, 40% of chip power was spent just driving the clocks. I'm sure it's better today, but how much? What about all the leakage in the SRAMs?



I don't have any stats on modern power consumption, but to be fair the P4 was an experiment in higher clock speeds that didn't pan out.

Future processors focused on increased parallelization and returned to less power-hungry clock speeds.




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