Hacker News
new
|
past
|
comments
|
ask
|
show
|
jobs
|
submit
login
rbanffy
on June 12, 2010
|
parent
|
context
|
favorite
| on:
MIT CADR (Lisp machine) emulator and software
So, anyone willing to risk an FPGA implementation?
samlittlewood
on June 12, 2010
[–]
There is some plausible verilog code on that page and schematics. It looks like Brad got a core design running in simulation - no evidence of synthesis or IO (yet?).
Tempting - amongst 1e6 other things.
rbanffy
on June 12, 2010
|
parent
[–]
Same here.
So much to do, so little free time...
Guidelines
|
FAQ
|
Lists
|
API
|
Security
|
Legal
|
Apply to YC
|
Contact
Search:
