I see one of the advantages being that it is very easy to learn due to its simplicity. There is also no need for complex instruction decoding placed on the hardware designer.

For software there may be a slight increase in complexity for control flow because it is necessary to specify the addresses where execution continues both when the condition is met and when it fails versus CISC which specifies only the address to branch to when the condition is met and defaults to the next instruction inline when it fails but there is also a gain in flexibility by specifying both addresses because you could, for example, call one subroutine for Z and call another subroutine for NZ and both would return to the next instruction inline.

When I first read about Move machines it appeared that they were very inefficient and the simple ones described were. In the decades since then I have devised means to offset that inefficiency with more powerful hardware functions. Especially with an FPGA target it is possible to perform complex functions in hardware that only needs to be memory mapped. Depending on your application you could have vector math, complex number math, or SIMD instructions which run in a single machine cycle. It is possible to have a shift-and-add multiplier which takes several cycles that can be loaded then you could perform some other operations while waiting for completion. I have written shift-and-add multiply routines for microprocessors which needed the processor to do the shifts and to do the adds which kept it fully occupied. While I do not claim that the design I have documented is the optimal processor, I maintain that it should have reasonable performance.

One of my goals in releasing this design is to draw interest and receive suggestions and recommendations for improving it from the highly intelligent community that reads HN and uses Github. I would like to see it optimized.