Your site mentions a lot of "FPGA", do you have some actual silicon prototypes?
What's the current raw speed in MHz or FLOPS?
I read about OpenRISC, OpenSPARC, RISC-V, Z-Scale, BOOM - which are furthest in testing phase? Can we buy some of them in 2017? Or will it take longer?
Our most recent update was releasing an untethered version of the Rocket core http://www.lowrisc.org/blog/2015/12/untethered-lowrisc-relea.... Our next development goals are integrating the minion cores and integrating with third-party IP in order to produce the initial test chip, which we're intending to tape out later this year.
We haven't yet produced a silicon prototype, but will be taping one out this year. The Berkelely Rocket implementation has been silicon-proven multiple times as has the ETH Zurich PULP core which we also hope to use. The aim of this test chip is to integrate an LPDDR3 memory controller+PHY, plus USB host controller+PHY.
I don't have the link handy, but the Rocket implementation has clocked at 1.5GHz on a 45nm process.
For the final question, perhaps it's useful to define some of these terms:
* OpenRISC: an older 32-bit open ISA.
* OpenSPARC: The open-sourced design from Oracle. GPL-licensed. I don't know of anyone planning to produce a commercially available ASIC using it.
* Z-scale and BOOM are both RISC-V implementations from Berkeley. Z-Scale is a microcontroller-class RISC-V implementation and BOOM is an out-of-order implementation. Both make use of parts of the Rocket implementation (essentially using the codebase as a library). I believe only the base Rocket design has been produced in silicon so far. With lowRISC, we hope to discuss at the upcoming RISC-V workshop (this Tuesday and Wednesday) the status of BOOM, and whether it will make sense to use it as our application cores.
I hope we'll see commercially available lowRISC chips towards the end of 2017, but we'll be able to make a better judgement about how realistic that is once we reach our first test chip.
"With lowRISC, we hope to discuss at the upcoming RISC-V workshop (this Tuesday and Wednesday) the status of BOOM, and whether it will make sense to use it as our application cores."
Hi Alex, I look forward to chatting with you guys about BOOM. =)
Definitely, looking forward to catching up with you and everyone else this week. With areas we're currently estimating, it seems we would have the area budget for 4x 2-wide BOOM cores (of course it's all quite rough at the minute). I'm keen to hear more on Tim Newsome's debug work and whether BOOM will also reap the rewards of it. See you Tuesday!
There has been one tape-out of Z-scale. An early iteration of it was used as a power management controller in one of our DVFS test chips. But we've made many changes since then and haven't taped it out since.
Can't really comment, since these aren't our projects. I haven't really seen any developments on these fronts, though.
> RISC-V, Z-Scale, BOOM
RISC-V is the ISA. Rocket, Z-Scale, and BOOM are implementations of the ISA we've produced at Berkeley. Rocket is our reference implementation. It is a 64-bit in-order core. Z-scale is a small 32-bit core with no MMU intended for microcontrollers. BOOM is an out-of-order 64-bit core. They all share some common code, but BOOM is a bit behind the other two.
We have taped out different Rocket and Z-scale chips. But these run as tethered systems and were only meant for our research. As a university research lab, we do not really have any intentions for mass manufacture. ASB can answer better about when lowRISC chips will be commercially available.
What's the current status? (I read http://www.lowrisc.org/blog/2015/06/second-risc-v-workshop-d... (June 30, 2015))
Your site mentions a lot of "FPGA", do you have some actual silicon prototypes?
What's the current raw speed in MHz or FLOPS?
I read about OpenRISC, OpenSPARC, RISC-V, Z-Scale, BOOM - which are furthest in testing phase? Can we buy some of them in 2017? Or will it take longer?