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Fast cores take exponentially more energy than slow ones. So the solution is to use more slow and simple cores instead. We get more performance per watt that way. On PCs we can use GPU's to make computations in parallel. I guess this is like that, but for servers.



GPUs are often considered "hard to program", let's see how this goes for FPGAs.


Intel suggests we program their GPUs and FPGAs with OpenCL. So, in theory, programming FPGAs could be not much harder than GPUs.


At some point we should be able to code these things in (a subset) of C++. Microsoft has made C++ AMP for GPU programming. Herb Sutter has said it or something similar has a good chance of being standardised in C++ at some point.

Some chatter along those lines:

http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/p006...


Good news then. There is no shortage of speedup when we stop considering all memory being equal.


>Fast cores take exponentially more energy than slow ones

What's your source for this/why does this happen?


From my fuzzy memory:

To make a cpu fast you need to shrink them. To the point that the "wires" in the core are so close together that electrons jump from one another. So there is lots of electrical interference. To overcome this voltage needs to be increased. This takes more power and makes the cpu hotter (which requires cooling).

But dont take my word for it. I did some quick Googling. Maybe you can find some better source and explanation:

https://en.wikipedia.org/wiki/Multi-core_processor#Technical...

"For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency. This is due to three primary factors:

- The memory wall; [...]

- The ILP wall; [...]

- The power wall; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "shrinking" the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall."


It is very well known that the out of order execution engine of modern cpu cores has a very high power overhead.

https://en.wikipedia.org/wiki/Out-of-order_execution

https://en.wikipedia.org/wiki/Bonnell_%28microarchitecture%2...


Basic logic: as you cram more and more out of order and parallel execution, branch prediction and other advanced techniques in a core, there is a diminishing return. If it weren't, you could create a single core of unlimited computing power.


I don't think it is exponential. Dynamic losses in a gate arise from a couple factors (shoot through, dissipation capacitance) but as far as I know they are a joules per switching event effect which scales linearly with clock.




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