Mentioning that a poc is successful only because of their colour is harsh. Maybe they bring value and have qualities that other candidates did not have. DEI only widens the pipeline, no private company lowers their standards.
The "well" has been poisoned for all such groups of people, and DEI as a concept will eventually be held accountable to the harm it did to the groups they supposedly aimed to help. DEI as a concept was a leech to society, feeding on good will and injecting itself everywhere. To the detriment of both sides, and almost never to the detriment of actual prejudiced individuals.
The company i work for does not have any quota and neither does meta. There is no lowering of standards to hire somebody, just more effort to get wider application pool and outreach programs to schools.
Also DEI is not just based on colour or ethnicity. There are other groups like mothers, neuro divergent people etc.
Part of the DNA of RISC-V is to provide a basis from which a million flowers can bloom. Instead of homebrewing, you can reuse RISC-V and make tweaks as you need... if you really do need a custom variant. Think of it as English, a common substratum from which there are lots of mostly interoperable dialects. This is what happened with Unix.
Now if we want a mainstream consumer then we will need a dominant strain or two. The RISC-V foundation is doing that with the RVA23 profiles etc, but if there is a few major ones that should be navigable. Linux had support for PC-98[1] which was a Japanese alternate x86 platform.
The changes I've seen proposed by Qualcomm don't seem drastically different [2], and could be incorporated in the same binaries with sniffing the supported features. The semantics are what are important, and it's not different there at all. Could be supported with trap and emulate
The code size reduction instructions are an extension that will go through and will eventually be supported by everyone, and is not the bone of contention here. They are designed to be "brown-field" instructions, that is, fit into the unimplemented holes in the current spec.
The reason the spec is going to split is not them, but the fact that Qualcomm also wants to remove the C extension, and put something else in the encoding space it frees.
Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now.
That said, if they implemented C, and then had their replacement toggleable with a CSR that would still be backwards (albeit not forwards) compatible so that'd only be an issue if Qualcomm RISC-V binaries become dominant, but I don't think binaries are gonna be that dominant outside of firmware going forward, and any that are will be from vendors that will multi-target.
>> Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now.
It may be low cost to decode a compressed instruction, but having them means regular 32-bit instructions can cross cache lines and page boundaries.
My own thought is that there should be a "next" version or RISC-VI that is mostly assembler-level compatible but changes all the instruction encodings to be more sane. What that means exactly is still a bit fuzzy, but I am a fan of immediate data being stored after the opcode.
> My own thought is that there should be a "next" version or RISC-VI that is mostly assembler-level compatible but changes all the instruction encodings to be more sane.
I feel like that is really a case of Chesterton's fence. It was done by people who litterally wrote the book on processor design (David Patterson, author of "Computer Architecture: A Quantitative Approach", "The Case for RISC", "A Case for RAID", ). I have heard a talk with the rationale behind where bits are placed to simplify low-end implementations.
> What that means exactly is still a bit fuzzy, but I am a fan of immediate data being stored after the opcode.
As a hobbyist, I get it... but except for when you are reading binary dumps directly, which happens so rarely these days, when is that ever relevant? That is just OCD. I think of this video when I get the same itch and temptation. https://www.youtube.com/watch?v=GPcIrNnsruc
Also, let's not forget that RISC-V is already a thing with millions of embedded units already shipped.
>> I feel like that is really a case of Chesterton's fence. It was done by people who litterally wrote the book on processor design
It was originally intended for use in education where students could design their own processors and fixed instruction sizes made that easier. I'm not saying "therefore it's suboptimal", just that there were objectives that might conflict with an optimal design.
>> > What that means exactly is still a bit fuzzy, but I am a fan of immediate data being stored after the opcode.
>> As a hobbyist, I get it... but except for when you are reading binary dumps directly, which happens so rarely these days, when is that ever relevant?
How about in a linker, where addresses have to be filled in by automated tools? Sure, once the weirdness is dealt with in code its "done" but it's still an unnecessarily complex operation. Also IIRC there is no way to encode a 64bit constant, it has to be read from memory.
Maybe I'm wrong, maybe it's a near optimal instruction encoding. I'd like to see some people try. Oh, and Qualcomm seems to disagree with it but for reasons that may not be as important as they think (I'm not qualified to say).
> Also IIRC there is no way to encode a 64bit constant, it has to be read from memory.
There never is, you can never set a constant as wide as the word length. Instead you must "build" it. You can either load the high bits as low, shift the value, and then add the low bits, or sometimes as Sparc has it ('sethi'), there is an instruction that combines the two for you.
THead says they've shipped several billion C906 and C910 cores, and those are 64 bit Linux applications cores, almost all of them with draft 0.7.1 of the Vector extension. The number of 32 bit microcontroller cores will be far higher (as it is with Arm).
yes, was curious why compression format didn't require
1. non compressed instructions are always 4 byte aligned (pad a 2 byte NOP if necessary, or use uncompressed 4 byte instruction to fix sizing)
2. jump targets are always 4 byte aligned (which exists without C, but C relaxes)
This avoids cache line issues & avoids jumps landing inside an instruction. Can consider each 2 compressed instructions as a single 4 byte instruction
Bit redundant to encode C prefix twice, so there's room to make use of that (take up less encoding space at least by having prefix be 2x as long), but not important
I completely agree. Not that everything has to be relaxed, but at least the things that made it impossible to decode RISC-V when C is enabled. The amount of code needed to detect when and how instructions are laid out is much larger than it should be.
It's a little easier than ARMv7, and orders of magnitude easier than x86, which doesn't seem to be preventing high performance x86 CPUs (at an energy use and surely silicon size penalty admittedly).
Everyone else in the RISC-V community except Qualcomm thinks the "C" extension is a good trade-off, and the reason Qualcomm don't is very likely because they're adapting Nuvia's Arm core to run RISC-V code instead, and of course that was designed for 4-byte instructions only.
That is a trade-off towards density that seems not worth it where all it would take is a 16 bit NOP to pad and a few more bytes of memory to save on transistors of implementation.
Maybe they did the actual math and figured it's still cheaper? Might be worth it.
Their argument is that since eventually there'll be 8 byte instructions, those will have the same cache line issues (tho that could be addressed by requiring 8 byte instructions be 8 byte aligned)
C is good for high performance instruction sets to. Funny how every company that starts with green field RISC-V doesn't ever mention it as a problem. And yet the one company who wants to leverage their ARM investment thinks its a huge problem that will literally break the currently established standard.
The solution to this is not to split, but just follow Qualcomm. Their vision for the future of the ISA is simply much better than SiFive's.
Right now, most devices on the market do not support the C extension, and any code that tries to be compatible does not use it. Qualcomm wants to remove it because it is actively harmful for fast implementations, and burns 75% of the entire encoding space, which is already extremely tight. SiFive really wants to keep it. The solution to fragmentation is to just disable the C extension everywhere, but SiFive doesn't want to hear that.
The expansion of a 16-bit C insn to 32-bit isn't the problem. That part is trivial. The problem (and it is significant) is for a highly speculative superscalar machine that fetches 16+ instructions at a time but cannot tell the boundary of instructions until they are all decoded. Sure, it can be done, but that doesn't mean that it doesn't cost you in mispredict penalties (AKA IPC) and design/verification complexities that could have gone to performance.
It is also true that burning up the encoding space for C means pain elsewhere. Example: branch and jump offsets are painfully small. So small that all non-toy code need to use a two instruction sequence to all call (and sometimes more).
These problems don't show up on embedded processors and workloads. They matter for high performance.
> Not fully decoded though, since it's enough to look at the lower bits to determine instruction size.
It is not about decoding, which happens later, it is about 32-bit instructions crossing the L1 cache line boundary in the L1-i cache which happens first.
Instructions are fetched from the L1-i cache in bundles (i.e. cache lines), and the size of the bundle is fixed for a specific CPU model. In all RISC CPU's, the size of a cache line is a multiply of the instruction size (mostly 32 bits). The RISC-V C extension breaks the alignment, which incurs a performance penalty for high performance CPU implementations, but is less significant for smaller, low power implementations where performance is not a concern.
If a 32-bit instruction cross the cache line boundary, another cache line must be fetched from the L1-i cache before an instruction can be decoded. The performance penalty in such a scenario is prohibitive for a very fast CPU core.
P.S. Even worse if the instruction crosses a page boundary, and the page is not resident in memory.
I don't think crossing cache lines is particularly much of a concern? You'll necessarily be fetching the next cache line in the next cycle anyway to decode further instructions (not even an unconditional branch could stop this I'd think), at which point you can just "prepend" the chopped tail of the preceding bundle (and you'd want some inter-bundle communication for fusion regardless).
This does of course delay decoding this one instruction by a cycle, but you already have that for instructions which are fully in the next line anyways (and aligning branch targets at compile time improves both, even if just to a fixed 4 or 8 bytes).
> I don't think crossing cache lines is particularly much of a concern?
It is a concern if a branch prediction has failed, and the current cache line has to be discarded or has been invalidated. If the instruction crosses the cache line boundary, both lines have to be discarded. For a high-performance CPU core, it is a significant and, most importantly, unnecessary performance penalty. It is not a concern for a microcontroller or a low power design, though.
Why does an instruction crossing cache lines have anything to do with invalidation/discarding? RISC-V doesn't require instruction cache coherency so the core doesn't have much restriction on behavior if the line was modified, so all restrictions go to just explicit synchronization instructions. And if you have multiple instructions in the pipeline, you'll likely already have instructions from multiple cache lines anyways. I don't understand what "current cache line" even entails in the context of a misprediction, where the entire nature of the problem is that you did not have any idea where to run code from, and thus shouldn't know of any related cache lines.
Mispredict penalties == latency of pipeline. Needing to delay decoding/expansion to after figuring out where instructions actually start will necessarily add a delay of some number of gates (whether or not this ends up in mispredict penalty increasing by any cycles of course depend on many things).
That said, the alternative of instruction fission (i.e. that which RISC-V avoids requiring) would add some delay too (I have no clue how these compare though, I'm not a hardware engineer; and RISC-V does benefit from instruction fusion which can similarly add latency, and whose requirement other architectures could decide to try to avoid (though it'd be harder to keep avoiding it as hardware potential improves while old compiled binary blobs stay unchanged), so it's complicated)
Ah, that makes sense, thanks.
I think on the end it all boils down to both the arm and the rv approach to be fine approaches, with slightly different tradeoffs.
> Qualcomm wants to remove it because it is actively harmful for fast implementations
Qualcomm's "fast implementation" reportedly started out life as an ARM core and has had it's decoders replaced. That explanation makes their very different use of the instruction space make much more sense to me than any other. They did the minimum to adapt an existing design. Not the stuff of lasting engineering.
> Right now, most devices on the market do not support the C extension
That's outright false.
And outside of the actual devices, the whole software ecosystem very much uses the C extension.
Qualcomm simply wants to break the standard to make money, that literally all it is.
> Qualcomm wants to remove it because it is actively harmful for fast implementations
Funny how not a single company other then Qualcomm argues this. Not Ventara, not Si-Five, not Esperanto, not Tenstorrent, non of the companies form China.
Its almost, almost as if it not that big of a deal and Qualcomm simply want to same money and reuse ARM IP.
> The solution to fragmentation is to just disable the C extension everywhere, but SiFive doesn't want to hear that.
Literally nobody except Qualcomm wants to hear it. It wasn't even a discussion before Qualcomm. All the other companies had plenty of opportunity to bring up issues in all the working groups, and nobody did. Literally not a single company gave a talk, talking about how the C extension was holding them back. In fact most of them were saying the opposite.
These things are supposed to be discuss in the open, its an open standards process. So please link me to the official statements by these companies that they are unhappy.
I have watched many discussions and updates by the work-groups, and nobody came forward.
And why are they afraid to come forward? If this is so important then shouldn't there be an effort to convince the community?
So sorry until I see something other claims like 'there is a shadow cabal of unhappy companies planning a takeover' I'm not gone buy that this is widespread movement.
It is important here because it takes away the moral high ground. It is also important because those who did it previously have not faced any repercussions, so why would anybody hesitate to do this.
I think people who use the word whataboutism do not understand the more difficult concept of hypocrisy. It's more difficult because it requires contextual reasoning.
"Whataboutism" is easy because it's purely syntactic, every time someone says "What about ...", you are allowed to accuse them of it--instead of having to confront, in good faith, an implied accusation of hypocrisy.
It's like Orwellian newspeak, but the new word is less expressive and more likely to confuse the disagreement.
I think people who engage in whataboutism and defend it with cries of "hypocrisy" do not understand the even more difficult concept that, even if you personally think that someone else is a hypocrite, it doesn't make you any less wrong.
Indeed, whataboutism itself is easy because it's purely distractional: "but Y is a hypocrite!" a defender of X may shout, when the topic is not Y, or their hypocrisy, but X, and what X did.
If your argument is that it was okay for X to do the thing, then you should be able to affirmatively say outright "I think it was okay for X to do the thing", and convincingly explain why, on a moral basis, it was okay for X to do the thing, without bringing anyone else into it.
Otherwise, it's like a child whining "but Stevie took a candy bar!" – maybe, maybe not, but that doesn't mean it's okay for you to take one, even if you think that makes someone a hypocrite
I believe most of the value in the ISA being open source would be captured by hyperscalars and companies like Qualcomm.
With companies like Qualcomm involved, I am afraid they are going to do the whole embrace, extend and extinguish strategy.
I believe SiFive's CPUs and chip designs are not open source generally, although they do open source a lot of related things such as software, specifications, tools. I looked at their GitHub and didn't find any CPUs in there, though there are a lot of repos.
Here's an interesting take on what someone thinks "open source" means in this context: gjsman-1000 wrote: Open source refers solely to the software side of things in these groups and types of projects. Thus, all of the drivers and software you need to use the SiFive is open source and thus you can say it is an open source design. However, it is not an "open hardware" design in that the IP used to design the chip is not released.https://news.ycombinator.com/item?id=25762114
I personally don't think of closed chip designs with open software and specifications as open source chips. That would be like saying Intel and AMD x86s are open source. Though to be fair to those companies, their CPU programming models are much more open than their FPGA programming models, which requires proprietary software and secret specifications to program them at all.
This seems to have been a prank to prove the contest was asham
But in much more "authentic" contest, what determines if a wine is better than another? Are they not just different taste and liking them or not is a person's subjective opinion, similar to food preference?
You, assuming you have no knowledge of wine, can absolutely tell the difference between truck stop $2.70 wine and a well made wine from a seasoned winemaker+vineyard+grapes+region. Yeah these awards are often hot air, but the claim that no one can tell the difference between well made wine and garbage wine is a joke. It's black and white, especially when you wake up the next day.
There are certain more 'objective' criteria used to judge wines. In fact one of the things you learn when learning to taste and judge wine is to try to separate what you like from judging if it is a well made wine.
A big one is complexity. Wines with a complex flavour profile (ie lots of different flavours) are generally judged as better than wines with a simple flavour profile. Another is length of finish. How long does a pleasant flavour linger in the mouth after swallowing. You can also judge how close the wine is to how a wine of that type is 'supposed' to taste, and how well the wine maker managed to achieve what they where trying to achieve. You might not particularly like Chianti, but you can still judge if the wine you are drinking is a really well made Chianti.
The RISC V fanboism is rampant here with bunch of them repeating their marketing slogan in the comments. There is nothing inevitable about RISC V. If anything it has lot of mountains to climb before it can be considered a challenge to the existing instruction set. It may or it may not do that. Being open does not automagically make it happen.
"Being open does not automagically make it happen." Absolutely true. Many many "open" things have never gained traction and have fallen by the wayside. It was a plausible argument about RISC-V in 2016. It is not in 2023, when it has already happened.
Lots of companies have made their decisions, projects are kicking off -- for example Samsung just started porting .NET and Tizen to RISC-V for use in their future TVs and other products. LG similarly. It will take five years for the products resulting from that to emerge, but they are coming.
The RISC-V ISA didn't even formally exist as a frozen spec a little over four years ago. Ratification in July 2019 was the starting gun for many to start projects. The results of that are just emerging in the last months -- the VisionFive 2, tne Lichee Pi 4A, the 64 core Milk-V Pioneer.
A lot more things have gone into the pipeline since then, and will be emerging in the next two to three years. Things up to around Apple M1 performance ... from multiple companies.
