The 6502 unfortunately relies on some effects that can't be described in FPGA synthesizable logic. You might get a lot of speed up over the extremely simplified spice style simulation you have to do that still might get you to real time, but it's not the slam dunk you might think.
It more or less falls under true classic highz buses with multiple drivers.
You have three options I can see
1) treat it as a spice simulation that aggressively optmizes to synthesizable logic most places other than the problem parts.
2) hand replace the problem parts with synthesizable logic sorta like how Nvidia replaces graphics shaders with had written replacements in their drivers
3) just throw the whole thing into a spice simulation
I think the decrement relies on open bus behavior I think - the 6502 uses it to cheat and set a value to FF in the same cycle which is then sent through the same path as increment or add, effectively adding -1 to a value.
